1. Field of the Invention
The present invention relates to electronic circuits, and more specifically to electronic circuits implementing RAM functionality.
2. Description of the Related Art
The active memory of modem computer systems relies heavily on the use of RAMs to perform active, volatile storage of both data and instructions. Static and dynamic RAMs are well known and well studied in the art. Dynamic memory is the work horse of the main memory array of most modern computer systems, while static memory is generally used in high speed memory caches, local to the primary processor.
The typical SRAM is composed of a large number of memory cells, each memory cell having a unique address within the memory. SRAM cells have typically been coupled to a pair of bit lines via a pair of word line transistors. When the word line signal has received a logical high signal assertion, data is exchanged between a pair of nodes internal to the SRAM cell and the pair of bit lines. The word line signal has generally been generated as a logical function of various bits of a received address. Depending on whether the operation is a read or a write, data is either transferred from the internal nodes of the RAM cell to the bit lines, or from the bit lines to the internal nodes of the RAM cell.
Sense amplifiers have typically been employed to increase the speed with which the bit line logic state changes (i.e., changes, in either voltages or currents, that represent transactions between logic states on the bit lines can be detected during reads). A sense amplifier has typically been constructed to detect small differences (i.e., the differential) in voltage or current between the bit lines of the bit line pair. The sense amplifier has typically contained a static CMOS transistor pair for each bit line with positive feedback. It drives the bit line with the higher logic state voltage to the positive rail and the bit line with the lower logic state to the negative rail.
However, even before input data arrives at the sense amplifier, small fluctuations between the bit lines may be detected. The fluctuations in the bit line may result from any of a variety of factors, including crosstalk from other memory cells and bit lines, electrical or switching noise, or other environmental factors. These fluctuations are overcome by the differential intentionally placed on the bit lines once the inputs arrive, but premature reading of the bit lines may inadvertently cause an erroneous measurement.
To reduce the chance of such an erroneous, premature reading, a delay circuit has typically been employed to delay the operation of the sense amplifier until the SRAM cell being read has had sufficient time to produce differential on the bit lines. The delay, typically originating from a clock edge, delays the triggering of the sense amplifier until the difference between the bit lines may be assumed to be caused by actual data from the RAM cell. The delay has sometimes been determined in a worse case scenario, i.e., to provide as much assurance as possible that the sense amplifier will not trigger early and thereby produce a false result. However, high performance SRAMs may incorporate some type of self timing.